Interconnecting structures for interconnecting layers of semiconductor material are typically employed in semiconductor integrated circuits. A prior art interconnecting structure is shown in FIG. 1 and comprises a bottom layer 12 crossed by a top layer 10, with contacts 22 formed on the bottom layer 12 at a lateral distance from the top layer 10, and a dielectric insulating layer 20 (not shown) separating the two layers 10, 12.
FIG. 2 shows a section taken along line A--A of FIG. 1. Besides the top layer 10 and the underlying bottom layer 12, the dielectric isolation layer 20 between the two layers 10, 12 can be seen, which isolates the two layers 10, 12 from each other. If the dielectric layer 20 is thin enough, a capacitance structure is obtained.
FIG. 3 shows a section taken along line B--B of FIG. 1 through the bottom layer 12. The contacts 22 are formed on the surface of the bottom layer 12 via conventional etching procedures. As can be seen, spacers 30 are formed at the sides of the bottom layer 12 during the etching procedure to form the top layer 10 (shown in FIG. 2). This is due to the fact that in the area of the edges of the bottom layer 12, the top layer 10 must be etched in double thickness. In other words, these spacers 30 are formed because in certain areas of the layers 10, 12, the entire coating, i.e., the sum of the thicknesses of layers 10 and 12, has to be etched away. As a result, if the etching is sufficiently anisotropic, the spacers 30 are left behind at the side surfaces of the bottom layer 12. Further, if a high-melting metal is then deposited by sputtering to form a silicide in order to achieve an improvement in the electrical characteristics of the arrangement, as is frequently done, the spacers 30 may cause short circuits to develop between the top layer 10 and the bottom layer 12 or oxide breakdowns may result.
Accordingly, it is the object of the present invention to substantially overcome and eliminate such disadvantages by providing an improved interconnecting structure for semiconductor integrated circuits that avoids the undesirable electrical characteristics associated with prior art interconnecting structures.